1. Field of the Invention
The present invention relates to a storage circuit of a signal processing unit which can keep a stored logic state even when power is off.
2. Description of the Related Art
A signal processing unit such as a central processing unit (CPU) has a variety of configurations depending on its application. A signal processing unit generally has some kinds of storage circuits such as a register and a cache memory as well as a main memory for storing data or a program. A register has a function of temporarily holding a data signal for carrying out arithmetic processing, holding a program execution state, or the like. In addition, a cache memory is located between an arithmetic unit and a main memory in order to reduce low-speed access to the main memory and speed up the arithmetic processing.
In a storage circuit, such as a register or a cache memory, of a signal processing unit, writing of a data signal needs to be performed at higher speed than in a main memory. In general, a flip-flop, a static random access memory (SRAM), or the like is used as a register or a cache memory. That is, a volatile storage circuit in which a data signal is erased when supply of power supply voltage is stopped is used for such a register, a cache memory, or the like.
In order to reduce power consumption, a method for temporarily stopping supply of a power supply voltage to a signal processing unit in a period during which a data signal is not input and output has been suggested (for example, see Patent Document 1). In the method disclosed in Patent Document 1, a nonvolatile storage circuit is located in the periphery of a volatile storage circuit, so that the data signal is temporarily stored in the nonvolatile storage circuit.